/**
  ******************************************************************************
  * @file    i2s.h
  * @author  hyseim software Team
  * @date    18-Aug-2023
  * @brief   This file provides all the tmp functions.
  ******************************************************************************
  * @attention
  *
  * Copyright (c) 2020 Hyseim. Co., Ltd.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */


/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __I2S_H__
#define __I2S_H__

/* Includes ------------------------------------------------------------------*/
#include "utils.h"

#ifdef __cplusplus
 extern "C" {
#endif

/** @addtogroup IM110GW_I2S_Driver
  * @{
  */

/** @addtogroup I2S
  * @{
  */


/* ================================================================================ */
/* ================              Inter-IC Sound (I2S)              ================ */
/* ================================================================================ */
typedef struct
{
    __IO uint32_t IER;              /*!< I2S Enable Register,                                 Address offset: 0x000 */
    __IO uint32_t IRER;             /*!< I2S Receiver Block Enable Register,                  Address offset: 0x004 */
    __IO uint32_t ITER;             /*!< I2S Transmitter Block Enable Register,               Address offset: 0x008 */
    __IO uint32_t CER;              /*!< Clock Enable Register,                               Address offset: 0x00C */
    __IO uint32_t CCR;              /*!< Clock Configuration Register,                        Address offset: 0x010 */
    __O  uint32_t RXFFR;            /*!< Receiver Block FIFO Reset Register,                  Address offset: 0x014 */
    __O  uint32_t TXFFR;            /*!< Transmitter Block FIFO Reset Register,               Address offset: 0x018 */
         uint32_t RESERVED0;        /*!< Reserved,                                                            0x01C */
    union {
    __I  uint32_t LRBR;             /*!< Left Receive Buffer Register,                        Address offset: 0x020 */
    __O  uint32_t LTHR;             /*!< Left Transmit Holding Register,                      Address offset: 0x020 */
    };
    union {
    __I  uint32_t RRBR;             /*!< Right Receive Buffer Register,                       Address offset: 0x024 */
    __O  uint32_t RTHR;             /*!< Right Transmit Holding Register,                     Address offset: 0x024 */
    };
    __IO uint32_t RER;              /*!< Receive Enable Register,                             Address offset: 0x028 */
    __IO uint32_t TER;              /*!< Transmit Enable Register,                            Address offset: 0x02C */
    __IO uint32_t RCR;              /*!< Receive Configuration Register,                      Address offset: 0x030 */
    __IO uint32_t TCR;              /*!< Transmit Configuration Register,                     Address offset: 0x034 */
    __I  uint32_t ISR;              /*!< Interrupt Status Register,                           Address offset: 0x038 */
    __IO uint32_t IMR;              /*!< Interrupt Mask Register,                             Address offset: 0x03C */
    __I  uint32_t ROR;              /*!< Receive Overrun Register,                            Address offset: 0x040 */
    __I  uint32_t TOR;              /*!< Transmit Overrun Register,                           Address offset: 0x044 */
    __IO uint32_t RFCR;             /*!< Receive FIFO Configuration Register,                 Address offset: 0x048 */
    __IO uint32_t TFCR;             /*!< Transmit FIFO Configuration Register,                Address offset: 0x04C */
    __O  uint32_t RFF;              /*!< Receive FIFO Flush Register,                         Address offset: 0x050 */
    __O  uint32_t TFF;              /*!< Transmit FIFO Flush Register,                        Address offset: 0x054 */
         uint32_t RESERVED1[90];    /*!< Reserved,                                                    0x058 - 0x1BC */
    __I  uint32_t RXDMA;            /*!< Receiver Block DMA Register,                         Address offset: 0x1C0 */
    __O  uint32_t RRXDMA;           /*!< Reset Receiver Block DMA Register,                   Address offset: 0x1C4 */
    __O  uint32_t TXDMA;            /*!< Transmitter Block DMA Register,                      Address offset: 0x1C8 */
    __O  uint32_t RTXDMA;           /*!< Reset Transmitter Block DMA Register,                Address offset: 0x1CC */
    __I  uint32_t COMPPARAM2;       /*!< Component Parameter Register 2,                      Address offset: 0x1F0 */
    __I  uint32_t COMPPARAM1;       /*!< Component Parameter Register 1,                      Address offset: 0x1F4 */
    __I  uint32_t COMPVERSION;      /*!< I2S Component Version Register,                      Address offset: 0x1F8 */
    __I  uint32_t COMPTYPE;         /*!< I2S Component Type Register,                         Address offset: 0x1FC */
    __IO uint32_t DMACR;            /*!< DMA Control Register,                                Address offset: 0x200 */
} I2S_t;

#define I2S      ((I2S_t*)(I2S_BASE))


/*------------------------------------------------------------------------------------------------------*/
/*---                                      Inter-IC Sound (I2S)                                      ---*/
/*------------------------------------------------------------------------------------------------------*/
/********************************  Bit definition for I2S_IER register  *********************************/
#define I2S_IER_IEN             (0x1U << 0)          /*!< I2S Enable */

/********************************  Bit definition for I2S_IRER register  ********************************/
#define I2S_IRER_RXEN           (0x1U << 0)          /*!< Receiver block enable */

/********************************  Bit definition for I2S_ITER register  ********************************/
#define I2S_ITER_TXEN           (0x1U << 0)          /*!< Transmitter block enable */

/********************************  Bit definition for I2S_CER register  *********************************/
#define I2S_CER_CLKEN           (0x1U << 0)          /*!< Clock generation enable/disable */

/********************************  Bit definition for I2S_CCR register  *********************************/
#define I2S_CCR_SCLKG_Msk       (0x7U << 0)          /*!< Gating of sclk field mask */
#define I2S_CCR_SCLKG_NONE      (0x0U << 0)          /*!< Clock gating is disabled */
#define I2S_CCR_SCLKG_12        (0x1U << 0)          /*!< Gating after 12 sclk cycles */
#define I2S_CCR_SCLKG_16        (0x2U << 0)          /*!< Gating after 16 sclk cycles */
#define I2S_CCR_SCLKG_20        (0x3U << 0)          /*!< Gating after 20 sclk cycles */
#define I2S_CCR_SCLKG_24        (0x4U << 0)          /*!< Gating after 24 sclk cycles */

#define I2S_CCR_WSS_Msk         (0x3U << 3)          /*!< No description */
#define I2S_CCR_WSS_16          (0x0U << 3)          /*!< 16 sclk cycles */
#define I2S_CCR_WSS_24          (0x1U << 3)          /*!< 24 sclk cycles */
#define I2S_CCR_WSS_32          (0x2U << 3)          /*!< 32 sclk cycles */


/********************************  Bit definition for I2S_RXFFR register  *******************************/
#define I2S_RXFFR_RXFFR         (0x1U << 0)          /*!< Receiver FIFO Reset */

/********************************  Bit definition for I2S_TXFFR register  *******************************/
#define I2S_TXFFR_TXFFR         (0x1U << 0)          /*!< Transmitter FIFO Reset */


/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/

/** @defgroup I2S_Exported_Constants
  * @{
  */

#define I2S_WordSelectSize_16   I2S_CCR_WSS_16
#define I2S_WordSelectSize_24   I2S_CCR_WSS_24
#define I2S_WordSelectSize_32   I2S_CCR_WSS_32

#define I2S_SclkGate_None       I2S_CCR_SCLKG_NONE
#define I2S_SclkGate_12         I2S_CCR_SCLKG_12
#define I2S_SclkGate_16         I2S_CCR_SCLKG_16
#define I2S_SclkGate_20         I2S_CCR_SCLKG_20
#define I2S_SclkGate_24         I2S_CCR_SCLKG_24

#define I2S_IT_RXDA   (0x01)
#define I2S_IT_RXFO   (0x02)
#define I2S_IT_TXFE   (0x10)
#define I2S_IT_TXFO   (0x20)

#define I2S_DataFormat_Ignore   ((uint32_t)0x00000000)
#define I2S_DataFormat_12b      ((uint32_t)0x00000001)
#define I2S_DataFormat_16b      ((uint32_t)0x00000002)
#define I2S_DataFormat_20b      ((uint32_t)0x00000003)
#define I2S_DataFormat_24b      ((uint32_t)0x00000004)
#define I2S_DataFormat_32b      ((uint32_t)0x00000005)

/**
  * @}
  */

/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/

void I2S_DeInit(void);
void I2S_Cmd(FunctionalState_t NewState);

void I2S_ReceiverCmd(FunctionalState_t NewState);
void I2S_TransmitterCmd(FunctionalState_t NewState);

void I2S_ClockConfig(uint32_t I2S_WordSelectSize, uint32_t I2S_SclkGate);
void I2S_ClockCmd(FunctionalState_t NewState);

void I2S_ReceiverFIFOFlush(void);
void I2S_TransmitterFIFOFlush(void);


uint32_t I2S_Channel_ReadLeftData(void);
uint32_t I2S_Channel_ReadRightData(void);

void I2S_Channel_WriteLeftData(uint32_t LeftData);
void I2S_Channel_WriteRightData(uint32_t RightData);

void I2S_Channel_ReceiveCmd(FunctionalState_t NewState);
void I2S_Channel_TransmitCmd(FunctionalState_t NewState);

void I2S_Channel_ReceiveConfig(uint32_t I2S_DataFormat);
void I2S_Channel_TransmitConfig(uint32_t I2S_DataFormat);

void I2S_Channel_ITConfig(uint8_t I2S_IT, FunctionalState_t NewState);
ITStatus_t I2S_Channel_GetITStatus(uint8_t I2S_IT);
void I2S_Channel_ClearITPendingBit(uint8_t I2S_IT);

void I2S_Channel_ReceiveFIFOConfig(uint8_t Threshold);
void I2S_Channel_TransmitFIFOConfig(uint8_t Threshold);

void I2S_Channel_ReceiveFIFOFlush(void);
void I2S_Channel_TransmitFIFOFlush(void);

/**
  * @}
  */

/**
  * @}
  */

#ifdef __cplusplus
}
#endif

#endif /* __IM110GW_I2S_H */
